EEPROMs or electrically-erasable, electrically-programmable ROMs, typically consist of an array of MOSFETs with a floating gate in case of double poly structure or with MNOS in case of single poly structure. In case of double poly floating gate structure, a typical cell consists of a substrate of a specified conductivity type with two heavily doped regions of an opposite conductivity type, formed on its face. The heavily doped regions, designated the drain and the source, are separated by a channel region. A thin oxide layer is grown on the surface of the channel and a floating gate is then formed on the thin oxide. A control gate, separated by a layer of an insulator, is formed across the floating gate.
To program the cell, appropriate voltages are applied to the source, drain and control gate to cause the floating gate to be charged by either hot electron injection or Fowler-Nordheim tunneling. The cell is read by placing proper read voltages on the source, drain and control gate, and sensing the current flow between the source and the drain. The channel of a programmed cell (a cell with a negative charge on the floating gate) will not conduct, storing a logic zero. Typically, EEPROM cells are erased by discharging the floating gate by applying erase voltages between the control gate, source, and drain, and discharging the floating gate by Fowler-Nordheim tunneling. The channel of an erased cell (a cell with zero or positive charge on its floating gate) will conduct, storing a logic one.
The formation of the source and drain diffused regions requires several steps. A conventional set of these steps includes defining the areas of the substrate in which the diffusion will be performed by depositing and patterning a photoresist on the overlying oxide layer and then etching the exposed oxide away. Then, following definition of the boundaries of the prospective diffused regions, the actual implant must be made. Thus, by eliminating heavily doped diffused source and drain regions, the process of manufacturing transistors can be simplified.
The advantages of reduced processing steps are greatly magnified when an array, such as a memory array, is being contemplated. The elimination of the source and drain diffusions will allow the array to be more scalable, with a consequent improvement in memory cell density. Further improvement in cell density can be achieved if adjacent cells can be electrically isolated from each other without intervening physical structure such as layers of insulator and/or channel stop implantations. Many prior art devices have relied on thick field oxide regions and channel stops to isolate adjacent columns of cells to avoid read and write disturb. Providing columns of cells which are self-isolating will allow elimination of these structures, allowing increased cell density on the chip since less space will be expended on isolating structure such as oxide regions and channel stops.